`timescale 1ns / 1ps

module rnd_generator_register_sim();
    reg [31:0] rnd_seed;
    wire [14:0] o0;
    wire [14:0] o1;
    wire [14:0] o2;
    wire [14:0] o3;
    wire [14:0] o4;
    
    rnd_generator_register UUT(rnd_seed, o0, o1, o2, o3, o4);
    
    initial begin
        rnd_seed = 13243415;
        #10 rnd_seed = 13243417;
        #10 rnd_seed = 13243419;
        #10 rnd_seed = 983784993;
        #10 rnd_seed = 983784995;
        #10 rnd_seed = 983784997;
        #10 $stop;
    end
endmodule
